PEB3265HV1.5

Product Summary

3 Description of Functional Blocks<br />
3.1 General Functions and Device Architecture<br />
Figure 4 shows the architecture of the ISAC-SX containing the following functions:<br />
? S/T-interface transceiver supporting the modes TE, LT-T, LT-S, NT and Intelligent NT<br />
? Different host interface modes:<br />
- Parallel microcontroller interface<br />
(Siemens/Intel multiplexed, Siemens/Intel non multiplexed, Motorola modes)<br />
- Serial Control Interface (SCI)<br />
? Optional indirect register address mode reduces number of registers to be accessed<br />
to two locations<br />
? One D-channel HDLC-controller with 64 byte FlFOs per direction with programmable<br />
FIFO block size (threshold) of 4, 8, 16 or 32 byte for receive direction and 16 or 32<br />
byte for transmit direction<br />
? Support of firmware download via one B-channel HDLC-controller and FlFOs with<br />
reduced functionality<br />
? IOM-2 interface for terminal (TE mode), linecard (LT-T or LT-S) or NT applications<br />
? IOM handler with controller data access registers (CDA) allows flexible access to IOM<br />
timeslots for reading/writing, looping and shifting data<br />
? Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots<br />
? Flexible timeslot assignment of HDLC controllers on IOM for IDSL support<br />
? MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange<br />
? C/I-channel handler and TIC bus access controller<br />
? D-channel access mechanism in all modes<br />
? D-channel priority handler on IOM-2 for intelligent NT applications<br />
? Capability to control the start of the multiframe for synchronization from external<br />
signals (M-bit input pin in LT-S/NT mode, M-bit output pin in TE, LT-T mode)<br />
? Auxiliary interface with interrupt and general purpose I/O lines and 2 LED drivers<br />
? LED connected to pin ACL indicates S-interface activation status automatically or can<br />
be controlled by the host<br />
? Level detect circuit on the S interface reduces power consumption in power down<br />
mode<br />
? Two timers for periodic or single interrupts (periods between 1 ms and 14.336 s)<br />
? Clock and timing generation<br />
? Digital PLL to synchronize the transceiver to the S/T interface<br />
? Buffered 7.68 MHz oscillator clock output allows connection of further devices and<br />
saves another crystal on the system board<br />
? Reset generation (watchdog timer)